The interfacing circuit therefore should be designed in such a way that it matches the memory signal requirements with the signals of the microprocessor. For example for carrying out a READ process, the microprocessor should initiate a read signal which the memory requires to read a data.
In simple words, the primary function of a memory interfacing circuit is to aid the microprocessor in reading and writing a data to the given register of a memory chip. We know that keyboard and Displays are used as communication channel with outside world. So it is necessary that we interface keyboard and displays with the microprocessor. In this type of interfacing we use latches and buffers for interfacing the keyboards and displays with the microprocessor.
But the main disadvantage with this interfacing is that the microprocessor can perform only one function. It functions as an input device if it is connected to buffer and as an output device if it is connected to latch. Thus the capability is very limited in this type of interfacing. Programmable peripheral devices were introduced by Intel to increase the overall performance of the system.
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It reduces the cost of decoding circuit, but it has a drawback of multiple addresses shadow addresses. The status of the other address lines is not considered, since those address lines are not used for generation of chip select signals. We have seen that wait states can be introduced in the machine cycles using READY signal to interface slower memory devices. In this section we are going to see the circuits for wait state generator and applications of those circuits to interface slower memories.
The Fig. This circuit generates single wait state in every machine cycle. The circuit operation is given below.
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